Block Level and Full chip RTL and Verification

Over the last decade, newer languages such as SystemVerilog have allowed verification engineers to significantly improve their productivity in building and maintaining complex verification environments. The availability of a large body of pre-verified components provided by standardized methodologies such as eRM, VMM, OVM and UVM have also helped significantly.

At Eximietas we have experience in building large maintainable verification environments in both SystemC and SystemVerilog. We can help to preserve your investment in legacy simulation environments or help you to build a new one from starting to inception.

Ineffective utilization of newer verification techniques in various verification organizations have led to the following problems:

• Increased use of license, compute and storage resources due to sub-optimal constraining of testbench stimulus.
• Lack of predictability in verification schedules

Our verification team has been successful at avoiding these problems by not relying purely on a single verification methodology. Based on the complexity of the design-under-test (DUT), we engage one or more of the following methods.

• Directed Test Cases
• Constrained Random Verification using golden reference models
• Assertion based verification
• Formal verification to validate “ASIC-style” DUT against a golden reference model

We also use code and functional coverage metrics throughout our verification cycle to conserve simulation resources and assure predictability of the schedule.